1. Technical Field
The present invention relates generally to a semiconductor memory apparatus, and more particularly, to a performance test on a sense amplifier in a semiconductor memory apparatus.
2. Related Art
A typical semiconductor memory apparatus includes a plurality of bit lines intersecting word lines to form memory cells. Phase-change random access memory (PRAM) is a type of semiconductor memory apparatus currently considered as having promise due to its ability to maintain information during the interruption of power, and since it possesses many of the desirable characteristics of dynamic random access memory (DRAM) apparatuses. A typical PRAM apparatus includes a plurality of memory cells each having one cell transistor connected to a word line and one variable resistor connected to a bit line. The variable resistor of the memory cell is manufactured using a special thin film material, such as a chalcogenide (Ge2Sb2Te5) alloy, functioning as a reversible phase change material. The variable resistor has electric characteristics in which resistivity becomes relatively high in an amorphous state and resistivity becomes relatively low in a crystal state. Therefore, the different states of the phase change material can be used to represent logic values of data, and data stored in a memory cell can be differentiated using the difference between the resistivities of the variable resistor. In other words, information can be written by setting the state in which the resistivity of the variable resistor becomes high at a digital logic value ‘1’ and a state in which the resistivity of the variable resistor becomes low at a digital logic value ‘0’. The reversible phase change of the variable resistor is made to occur by Joule heat which is generated by applying electric pulses from the outside. As such, a process of controlling the phase change of the variable resistor is referred to as Set/Reset. Therefore, a PRAM type semiconductor memory apparatus can serve as a non-volatile memory apparatus.
In a typical semiconductor memory apparatus, a sense amplifier is not required for each memory cell; and instead, one sense amplifier is typically required for a plurality of memory cells. Each memory cell is connected to the sense amplifier through the bit line, and the sense amplifier functions to amplify current of the bit line during the data output operation. A configuration for the discharge of current remaining in the bit line is further provided in the memory cell region. The bit line discharge operation should be performed immediately before the data input operation is performed.
An important issue of semiconductor memory apparatuses is the defect rate. It is confirmed that the defects often occur in the memory cells within the core region. Herein, it is estimated that the characteristics of the sense amplifier is a cause of defects occurring in the memory cells. However, a method of testing the characteristics of the sense amplifier is not known to exist. In other words, a designer does not have a method in which it can be determined whether the sense amplifier can amplify current to a certain degree. Therefore, it is not easy to understand the cause of the defects occurring in the memory cells. As a consequence, it is impossible to test the characteristics of the sense amplifier using conventional configurations of the semiconductor memory apparatus. The difficulties in determining the cause of defects makes it difficult to design solutions for improving the defect rate.